category: gate array circuits

Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment

... Figure 4. Arrhenius plot of area leakage at a reverse voltage of 0.5 V, for three different halo conditions (22). The perimeter leakage JP shows a similar dependence on n-type counterdoping (Figure 5). The activation energy of JP in ...

Advanced Gate Stack, Source/drain, and Channel Engineering for Si-based CMOS 2: New Materials, Processes and Equipment

Fred Roozeboom

Gate array circuits

... (110) PMOS transistors. EXPERIMENT Figure 1 illustrates the process flow for the DSO integration. The starting wafer ... CMP 5. Silicon CMP 5. Silicon CMP -0.4 -0.8 Gate bias (V). 364 ECS Transactions, 3 (2) 363-369 (2006). Nitride Nitride ...